Bernd Becker. Partner at Warth & Klein Grant Thornton AG. Warth & Klein Grant ThorntonJohannes Gutenberg-Universität Mainz / University of Mainz. Bernd Becker (* in Hermeskeil) ist ein deutscher Informatiker und Hochschullehrer. Becker studierte von 19Mathematik an der Universität des. Dachdeckermeister in Heusweiler und Ottweiler bei Dachdeckermeister Bernd Becker.
Bernd Becker (Informatiker)bernd becker uni freiburg. Bernd Becker ist der Name folgender Personen: Bernd Becker (Schriftsteller) (Pseudonym Bernd Beckstrat; –nach ), deutscher Kaufmann und. Bernd Becker ist ein deutscher Informatiker und Hochschullehrer. Becker studierte von 19Mathematik an der Universität des Saarlandes und promovierte dort zur Graphentheorie. Von 19forschte und lehrte er mit kurzen.
Bernd Becker Areas of expertise VideoCloud for Europe, session 2a -- Bernd Becker (Eurocloud, Chairman)
Eine solche Blockade lasse One Ui 2.1 relativ Bernd Becker umgehen und mache somit Joachim Klöckner Zugriff auf die (illegale) Seite wieder mglich. - Saarländisches FamilienunternehmenNeuer Abschnitt Teaser Bennent Schauspieler im WDR - Der Podcast mehr WDR 5 - kompetent, gründlich, klar mehr.
Januar 2018 in den Bernd Becker Kinos. - Auswahl MediathekBuch erstellen Als PDF herunterladen Druckversion. Bernd Becker holds the position of Chairman for ThyssenKrupp Drauz Nothelfer GmbH and Chief Executive Officer at ThyssenKrupp MetalCutting GmbH. He previously occupied the position of Chief Executive Officer for Thyssenkrupp System Engineering GmbH and Chief Executive Officer of Cross Hueller GmbH. Bernd is an honest person and understands the importance of business relationships. The projects we have worked on for the past seven years, went smooth due to the knowledge and thoroughness he. The research activities of Bernd Becker have been primarily in the area of computer-aided design, test and verification of (digital) circuits and systems (VLSI CAD). A focus of his research is the development and analysis of efficient data structures and algorithms in VLSI CAD. Bernd Becker A new dynamically consistent synthetic event set of European windstorm footprints (SFP) with characteristics comparable to station observations has been developed in collaboration. Bernd Becher and Hilla Becher, Bernd Becher in full Bernhard Becher, Hilla Becher née Wobeser, (respectively, born August 20, , Siegen, Germany—died June 22, , Rostock; born September 2, , Potsdam, Germany—died October 10, , Düsseldorf), German photographers known for their straightforward black-and-white images of types of industrial buildings. Bernd Becker ist ein deutscher Informatiker und Hochschullehrer. Becker studierte von 19Mathematik an der Universität des Saarlandes und promovierte dort zur Graphentheorie. Von 19forschte und lehrte er mit kurzen. The research activities of Bernd Becker have been primarily in the area of computer-aided design, test and verification of (digital) circuits and systems (VLSI CAD). Bernd Becker (* in Hermeskeil) ist ein deutscher Informatiker und Hochschullehrer. Becker studierte von 19Mathematik an der Universität des. Bernd Becker ist der Name folgender Personen: Bernd Becker (Schriftsteller) (Pseudonym Bernd Beckstrat; –nach ), deutscher Kaufmann und.
The resulting subproblems are solved and merged incrementally, reusing not only intermediate local optima, but also additional constraints which are derived from solving the individual subproblems by the back-end SAT solver.
Extensive experimental results for the last MaxSAT evaluation benchmark suitew demonstrate that our encoding is in general smaller compared to existing methods using a monolithic encoding of the constraints and converges faster to the global optimum.
The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability.
As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level.
The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency.
Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.
Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker Efficient SAT-based Circuit Initialization for Large Designs Int'l Conf.
Specifically, we consider the following two problems: 1 Determine a sequence that initializes a maximal set of flip-flops starting in a completely unknown state.
The underlying principle of our methods is a maximization formalism using formal optimization techniques based on satisfiability solvers MaxSAT.
We introduce several heuristics which increase the scalability of our approach significantly. Experimental results demonstrate the applicability of the method for large academic and industrial benchmark circuits with up to a few hundred thousand gates.
Our algorithm is based on two key ingredients: a graph decomposition into strongly connected subgraphs combined with a novel factorization strategy for polynomials.
Experimental evaluations show that these approaches can lead to a speed-up of up to several orders of magnitude in comparison to existing approaches.
Tobias Schubert, Marc Pfeifer, Bernd Becker Accurate Controlling of Velocity on a Mobile Robot 29th International Conference on Computers and Their Applications Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernadi, Matteo Sonza Reorda, Bernd Becker An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults Conf.
However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking.
We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences i.
We verify our approach by evaluating the miniMIPS microprocessor. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.
Yet it is unknown how to find stimulation patterns that produce desired results with the least interference. Towards this goal, we tested a generic closed-loop paradigm that autonomously optimizes stimulation settings.
We used neuronal networks coupled to a reinforcement learning based controller to maximize response lengths. In contrast to traditional model checking, probabilistic counterexamples are sets of finite paths with a critical probability mass.
Such counterexamples are not obtained as a by-product of model checking, but by dedicated algorithms. We define what probabilistic counterexamples are and present approaches how they can be generated.
We discuss methods based on path enumeration, the computation of critical subsystems, and the generation of critical command sets, both, using explicit and symbolic techniques.
Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker Efficient SMT-based ATPG for Interconnect Open Defects Conf.
However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered.
Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy.
This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations.
It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values.
Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude.
The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit, and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation which are free of any simulation pessimism in presence of unknowns.
The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected or possibly detected.
The pessimism w. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show, that by accurate analysis the number of detected faults can be significantly increased without increasing the test set size.
Making each FPGA uniquely identifiable, they allow for protection of intellectual property IP or generation of secret encryption keys.
Their implementation has been widely discussed, but most experiments have been conducted on Xilinx platforms.
In this paper, we report the statistical results from an analysis spanning 20 Cyclone IV FPGAs with 60 nm technology.
We parameterize the RO length, placement, ambient temperature, and non-PUF switching activity and discuss the observed effects on PUF quality.
The iSAT algorithm tightly integrates interval constraint propagation into the conflict-driven clause-learning framework.
During the solving process, this may result in a huge implication graph. This paper presents a method to compress the implication graph on-the-fly.
Experiments demonstrate that this method is able to reduce the overall memory footprint up to an order of magnitude. They represent an important and powerful way to model a wide range of complex real-life systems.
However, such models tend to be large and difficult to handle, making abstraction and abstraction refinement necessary. In this paper we present an abstraction and abstraction refinement technique for Markov automata, based on the game-based and menu-based abstraction of Markov decision processes.
First experiments show that a significant reduction in size is possible using abstraction. In this paper, we propose the usage of minimal critical subsystems of discrete-time Markov chains and Markov decision processes as counterexamples for violated omega-regular properties.
Minimality can thereby be defined in terms of the number of states or transitions. This problem is known to be NP-complete for Markov decision processes.
We show how to compute such subsystems using mixed integer linear programming and evaluate the practical applicability in a number of experiments.
They show that our method yields substantially smaller counterexample than using existing techniques. A counterexample is a symbolic representation of a sub-DTMC that is incrementally generated.
The crux to this incremental approach is the symbolic generation of paths that belong to the counterexample. We consider two approaches.
First, we extend bounded model checking and develop a simple heuristic to generate highly probable paths first. We then complement the SAT-based approach by a fully multi-terminal BDD-based technique.
All symbolic approaches are implemented, and our experimental results show a substantially better scalability than existing explicit techniques.
Dominik Erb, Karsten Scheibler, Michael Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic Int'l Test Conf.
Recently, an ATPG algorithm based on quantified Boolean formula QBF has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness.
In this paper, we consider ATPG based on restricted symbolic logic RSL and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG.
Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm.
An optimized version of RSL ATPG together with accurate fault simulation is up to x faster than the QBF-based solution, more scalable and more robust.
Derived from the SMT solver iSAT3 we present the solver iSAT3p that on the one hand allows the efficient handling of huge pseudo-Boolean constraints with several thousand summands and large integer coefficients.
On the other hand, experimental results demonstrate that at the same time iSAT3p is competitive or even superior to other solvers on standard pseudo-Boolean benchmark families.
Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker Using MaxBMC for Pareto-Optimal Circuit Initialization Conf.
Our approach combines techniques from symbolic SAT-based Bounded Model Checking BMC and incremental MaxSAT, leading to the first MaxBMC solver.
In traditional BMC safety and liveness properties are validated. We extend this formalism: in case the required property is satisfied, an optimization problem is defined to maximize the quality of the reached witnesses.
Further, we compare its qualities in different depths of the system, leading to Pareto-optimal solutions.
We state a sound and complete algorithm that not only tackles the optimization problem but moreover verifies whether a global optimum has been identified by using a complete BMC solver as back-end.
As a first reference application we present the problem of circuit initialization. Additionally, we give pointers to other tasks which can be covered by our formalism quite naturally and further demonstrate the efficiency and effectiveness of our approach.
Sein fortlaufendes Ziel ist die Erforschung von Möglichkeiten, die universitäre Lehre - insbesondere Vorlesungen mit über hundert Studierenden - durch den Einsatz von IT zu bereichern.
Hierfür wurden Apps für Studierende und Dozierenden entwickelt, die auf allen gängigen Geräten laufen. Die konzeptionelle Planung liegt bei einem interdisziplinären Team aus Informatikern und Instructional Designern; für die Implementierung wird eng mit einem studentischen Entwicklerteam zusammen gearbeitet.
Zwei Preisauszeichnungen zeigen die positive Resonanz, die SMILE bisher hervor gerufen hat. In diesem Workshop-Paper beschreiben wir den bisherigen Verlauf des Projekts und die Kernfunktionalitäten der Software.
Physically unclonable functions PUFs take advantage of subtle variations in the devices' production process to achieve this.
A ring oscillator RO PUF exploits differing time delays of circuits to yield a unique response from each device. The implementation of RO PUFs on FPGAs has been widely discussed but most experiments have been conducted on Xilinx FPGAs.
In this paper we are reporting statistical results from an analysis spanning 20 equivalent Altera FPGAs. The presented results include the PUF quality's dependency on different parameters like RO length and placement on the FPGA.
We identify the optimal RO length of 16 Logic Elements LE and show some specific placement cases for which the otherwise very good PUF quality decreases drastically.
We describe a new methodology to assess the vulnerability to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and their detection status expressed as Boolean satisfiability SAT formulae.
Vulnerability is quantified based on the number of solutions of such formulae, which are computed by an eficient SAT solver.
We demonstrate the applicability of this method by analyzing a sequential pseudo random number generator and a combinatorial multiplier circuit both protected by robust error-detecting codes.
While iSAT is efficient in finding unsatisfiability, on satisfiable instances it often terminates with an interval box whose satisfiability status is unknown to iSAT.
The CAD method, in turn, always terminates with a satisfiability result. However, it has to traverse a double-exponentially large search space. A symbiosis of iSAT and CAD combines the advantages of both methods resulting in a fast and complete solver.
This proves to be particularly beneficial for a CAD implementation designed to search a satisfying assignment pointedly, as opposed to search and exclude conflicting regions.
Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub Accurate Computation of Sensitizable Paths using Answer Set Programming Int.
For instance, such path sets can be used in the emerging areas of Post-silicon validation and characterization and Adaptive Test.
We present an ASP-based method for computing well-defined sets of sensitizable paths within a length range. Unlike previous approaches, the method is accurate and does not rely on a priori relaxations.
Experimental results demonstrate the applicability and scalability of our method. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three- or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.
In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests.
Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources.
The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean QBF satisfiability techniques to compute the possible signal states in the circuit accurately.
Efficient encoding of the problem instance ensures reasonable runtimes. We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.
For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults.
Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably.
Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker Accurate QBF-based test pattern generation in presence of unknown values Conf.
Sources of X-values are for example black boxes, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements.
To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs.
In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability SAT or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable.
This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values.
It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula QBF satisfiability.
The resulting improvement of fault coverage is shown on experimental results based on ISCAS benchmark and larger industrial circuits. The properties required are inserted as target of a bounded model checking BMC problem, by using Craig interpolants it can be stated whether sequences justifying the properties exist or not.
The initial state is either completely or partially unknown, and for the latter we engage a MAX-SAT formulation to retrieve the shortest sequence if a maximal subset of the initial state bits are unknown.
We apply this method to problems arising from digital circuit testing domain, in which usually an arbitrary initial state is assumed, i.
However, since some of these states may be unreachable during normal operation, this results in undesired secondary test conditions. In this paper BMC is used to 1 test timing faults in a digital circuit, thereby the test requirements are encoded as target properties.
Our method yields the shortest functional test-sequences that justify the target properties or it proves that such a sequence does not exist.
Furthermore, 2 the initialization of circuits is considered. We present a method that yields two-pattern tests sensitizing long paths while at the same time minimizing weighted switching activity.
Experimental results on standard benchmark circuits demonstrate the applicability of the method. We also demonstrate that the derived ELF signatures can be successfully detected using a clock control technique.
Our results can be utilized to overcome scaled-CMOS reliability challenges in several ways: 1. Low-cost ELF detection during on-line operation of robust systems without requiring expensive redundancy-based error detection techniques; 2.
Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung-Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker Early-Life-Failure Detection using SAT-based ATPG Int'l Test Conf.
Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs.
Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability.
Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely.
In this paper, we present an automatic test pattern generation ATPG technique based on Boolean Satisfiability SAT for detecting ELF-induced delay changes at all gates in a given circuit.
Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection.
We also demonstrate the robustness of our approach to manufacturing process variations. Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths Conf.
Using one test pair per path may lead to impractical test set sizes and test application times due to the large number of near-critical paths in state-of-the-art circuits.
Areas of expertise Ensemble prediction. Long-range forecasting. Large-scale synoptic weather types. Tropical cyclone forecasts.
Weather hazard prediction. Als Ihr Sicherheits-, Umwelt- und Energie-Experte bin ich Ihr Ansprechpartner rund ums Haus. Copyright c schornsteinfeger-roedelheim.
They exhibited their work in sets or typologies, grouping of several photographs of the same type of structure.
Well technically yes, but their work has also been referred to as sculpture. Overlooked beauty and the relationship between form and function.
Their first photobook Anonymous Sculptures was published in and is their most well-known body of work. They were often labelled as conceptual artists and influenced minimalist and conceptual artists like Ed Ruscha , Carl Andre and Douglas Huebler.
As professors of The Dusseldorf School of Photography , they influenced a generation of German photographers who were their students including Andreas Gursky , Candida Höfer , Thomas Ruff and Thomas Struth.
Member of the Scientific Directorate, Leibniz Center for Informatics, Schloss Dagstuhl. Member of Steering Committee: IEEE International Workshop on Reliability Aware System Design and Test RASDAT.
Co-Speaker of the Transregional Collaborative Research Center 14 Automatic Verification and Analysis of Complex Systems AVACS. Member of the Organizing Committee of ICCD International Conference of Computer Design.
Fellowship for Innovations in University Teaching Baden-Württemberg Stiftung, Joachim Herz Stiftung und Stifterverband für die Deutsche Wissenschaft.
IEEE Fellow for contributions to the development of algorithms and data structures for testing and verification of integrated circuits. Patent DE Schneller, leicht generierbarer und leicht testbarer VLSI Addierer;Both the number of aborts and the total runtime Krystal Vee significantly reduced compared to the state-of-the-art pure RSL-based algorithm. Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker Small-Delay-Fault ATPG with Waveform Accuracy Int'l Conf. Michael Collins, The Long Look. On a domain of partial design benchmarks, engaging incremental QBF methods significant performance gains over non incremental Rp Landesschau can be achieved. The number of solutions is precisely calculated by a SAT solver and can be translated into an exact vulnerability measure. Michael Collins. Here, we disprove realizability, that is, we prove Zuverlässiges Auto an unsafe state is reachable Rezept Für Goldene Milch matter how the blackboxes are implemented. Here we are sharing first tendenciesalready One Ui 2.1 and details of the conception and the ongoing development phases. The approach presented in this paper follows the latter line of interval-based reasoning, but extends it by including bitwise integer operations Kinoger.De cast operations between integer and floating-point arithmetic. In traditional BMC safety and liveness properties are validated.